1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Background Art
FIG. 4 shows a layout diagram of a memory cell array of a DRAM (Dynamic Random Access Memory), which is one type of semiconductor memory device designed using a conventional process for a DRAM integrated chip. In FIG. 4, bit lines formed of first layer aluminum wires are denoted as 1a to 1h. Word lines, formed of polysilicon wires, aligned in the direction crossing the bit lines for working as gate electrodes of the transistors that selectively connect memory cells to bit lines are denoted as 2. In addition, bit line contacts for electrically connecting bit lines 1 to memory cell transistors 5 are denoted as 3, memory cell capacitors are denoted as 4 and memory cell transistors are denoted as 5. 1Tr1C-type memory cells arranged at respective points of intersection of word lines 2 and bit lines 1, and formed of memory cell capacitors 4 and memory cell transistors 5, are denoted as 6, wherein memory cells 6 are connected to word lines 2 and bit lines 1.
In a conventional semiconductor memory device formed as described above, the resistance of polysilicon that forms word lines 2 is high and, therefore, it takes a very long time for data of a memory cell 6 to be transferred to a bit line 1 after application of a drive signal to a word line 2 has been started so that high speed memory operation is hampered in the case that word lines 2 are long.
In such a configuration, propagation delay of a signal from the driving end to the terminal end of a word line 2 is great and, therefore, a word line strap structure (word shunt structure) is used in order to limit to the minimum such delay. In a DRAM wherein such a word line strap structure is used, propagation delay of drive signals is prevented by strapping word lines 2 to upper layer low resistance metal wires (second layer aluminum wires), which become strapped wires formed according to the same pitch as word lines 2.
In recent years, a multi-layer wire structure has been adopted in place of conventional single-layer wires in the layout for DRAMs in order to reduce cell array size by narrowing the pitch of the wire pattern so as to achieve high integration. The distance between bit lines becomes very narrow in a DRAM wherein a multi-layer wire structure has been adopted. Therefore, strap contact regions become larger than the dimensions between wires, which are simply determined by the size of memory cells, in a memory cell array portion. In addition, contacts for strap connections (strap contacts) are formed of the same wire layer as the bit lines (first layer aluminum wires, for example) and, therefore, there is a defect wherein the distance between bit lines must be widened by providing sufficient space between memory cells as a result of enlargement of the total size of the memory cells in order to secure space for providing strap contacts for each memory cell.
That is to say, in recent years, DRAMs have three-dimensional structures, such as a stacked (layered) type or a trench type where special processes are used so as to achieve high integration and high capacitance in order to secure a large capacitance value in a small area for the capacitor structure of memory cells in comparison with the conventional planar-type capacitor and, thereby, though memory cells can be formed in a small area, the intervals between bit lines become too narrow for strap contacts to be provided for each memory cell, so that the configuration for strap connection can only be adopted by separately providing strapping regions at the ends of the memory cell array.
Though a word line strap structure that can prevent word line signal delays formed of polysilicon having a high resistance must be used in order to enable high speed memory operation in the above described manner, a problem arises wherein it is necessary to separately provide strapping regions at the ends of the memory cell array for the use of a word line strap structure and, thereby, an increase in the area of the memory cell array is caused.
In addition, a power supply line for supplying the power supply voltage to each memory cell is conventionally formed of a wire layer, which is a layer above bit lines, and the power supply voltage is supplied to each memory cell by making a contact to this upper layer power supply line and, therefore, there is a problem wherein the IR drop becomes large.
An object of the present invention is to provide a semiconductor memory device that allows high speed memory operation without causing an increase in the area of the memory cell portion.
Another object of the present invention is to provide a semiconductor memory device that can reduce the IR drop.
A semiconductor memory device of the present invention is provided with: word lines, making up a plurality, aligned parallel to each other; bit lines, making up a plurality, aligned parallel to each other in the direction crossing the word lines; memory cells, making up a plurality, connected to the word lines and to the bit lines; strap lines, making up a plurality, located above the word lines; and contacts, making up a plurality, formed between the bit lines for electrically connecting the word lines to the strap lines.
According to this configuration, the contacts for connecting the word lines to the strap lines are provided between the bit lines and it is not necessary to separately provide strapping regions at the ends of the memory cell array portions (plurality of memory cell regions) and it is not necessary to increase the intervals between memory cells by increasing the size of memory cells according to a standard CMOS process layout and, therefore, contacts for strapping word lines can be provided for each memory cell without the necessity of increase in the areas of the memory cell array portions or increase in the chip area and, thereby, propagation delay of drive signals of word lines can be prevented and high speed memory operation can be implemented.
In this case, each memory cell may be formed of a MOS transistor and a MOS capacitor and, thereby, the pitch between memory cells becomes large and the intervals between bit lines become large so that the contacts for strapping the word lines can easily be arranged between the bit lines.
In accordance with another aspect, a semiconductor memory device of the present invention is provided with: word lines, making up a plurality, aligned parallel to each other; bit lines, making up a plurality, aligned parallel to each other in the direction crossing the word lines; memory cells, making up a plurality, connected to the word lines and to the bit lines; and metal wires, making up a plurality, formed between the bit lines so as to be parallel to the bit lines for electrically connecting the memory cells to a power supply line.
According to this configuration, metal wires connected to the power supply line, which is in an upper layer, are provided between the bit lines and it is not necessary to increase the intervals between the memory cells by increasing the size of the memory cells according to a standard CMOS process layout in order to align these metal wires and, therefore, increase in area of the memory cell array portions and increase in chip area are not necessary. Thus, the power supply voltage is supplied to the memory cells from the metal wires connected to the power supply line and provided between the bit lines and, therefore, the IR drop of the power supply line can be reduced. In addition, the metal wires are formed parallel to the bit lines and, therefore, function as shield lines for reducing noise along the bit lines.
In this case, each memory cell may be formed of a MOS transistor and a MOS capacitor and, thereby, the pitch between memory cells becomes large and the intervals between bit lines become large so that the metal wires connected to the power supply line can easily be aligned between the bit lines.
In accordance with another aspect, a semiconductor memory device of the present invention is provided with: word lines, making up a plurality, aligned parallel to each other; bit lines, making up a plurality, aligned parallel to each other in the direction crossing the word lines; memory cells, making up a plurality, connected to the word lines and to the bit lines; strap lines, making up a plurality, aligned above the word lines; contacts, making up a plurality, formed between the bit lines so as to electrically connect the word lines to the strap lines; and metal wires, making up a plurality, formed between the bit lines so as to be parallel to the bit lines for electrically connecting the memory cells to a power supply line, wherein the contacts and the metal wires are arranged in an alternating manner between the bit lines.
According to this configuration, the contacts for connecting word lines to strap lines and metal wires connected to the power supply line are arranged, in an alternating manner, between bit lines and, therefore, the area of memory cell array portions and the chip area are not increased in order to arrange the contacts or metal wires so that high speed memory operation can be implemented and reduction in the IR drop of the power supply line and reduction in noise along the bit lines can be achieved.
In this case, each of the memory cells may be formed of a MOS transistor and a MOS capacitor and, thereby, the pitch between memory cells is increased and the intervals between bit lines also is increased so that the contacts for strapping word lines and metal wires connected to the power supply line can easily be arranged between the bit lines.